Device Modeling for Analog and RF CMOS Circuit Design

A driving force behind this fantastic progress is the long-term commitment to a steady downscaling of MOSFET/CMOS technology needed to meet the requirements on speed, complexity, circuit density, and power consumption posed by the many advanced applications relying on this technology. The degree of scaling is measured in terms of the half-pitch size of the first-level interconnect in DRAM technology, also termed the “technology node” by the International Technology Roadmap for Semiconductors. At the time of the 2001 ITRS update, the technology node had reached 130 nm, while the smallest features, the MOSFET gate lengths, were a mere 65 nm. Within a decade, these numbers are expected to be close to 40 nm and 15 nm, respectively.

Very important issues in this development are the increasing levels of complexity of the fabrication process and the many subtle mechanisms that govern the properties of deep submicrometer FETs. These mechanisms, dictated by device physics, have to be described and implemented into circuit design tools to empower the circuit designers with the ability to fully utilize the potential of existing and future technologies.



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