ΣΔ (Sigma Delta) A/D CONVERSION FOR SIGNAL CONDITIONING

Moore’s Law predicts a decrease by a factor of two in the feature size of CMOS technology every three years and has been valid for years. It implies a doubling of the operation speed and a four times higher transistor count per unit of area, every three years. The combination leads to an eight times higher processing capability per unit of area. This on-going miniaturization allows the integration of complex electronic systems with millions of transistors (Very-Large-Scale-Integration) and enables the integration of electronic systems.



The heart of the system is the signal processing core. This core supports a wide variety of functions, such as customization and programmability of multiple applications, channel coding, the definition of the user interface, etc. These functions are enabled by DSP, a controller CPU and various blocks of memory. In advanced ICs these blocks provide (almost) all signal processing and usually dominate in the overall power and area consumption of integrated systems. The huge data rates involved, require high-speed busses for communication between these blocks. A power-management unit fuels the system by providing the appropriate
supply voltages and currents.


Communication with the physical world is realized by a chain of mixed-signal, analog and RF-circuitry. This chain acts as a “signal-conditioning channel”. It translates physical signals into binary representations or vice versa. This channel also comprises amplification, filtering and possibly frequency translation. It is the challenge of present day mixed-signal and RF design to integrate the signal-conditioning channel at a low power consumption and a high performance level.




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